Verilog实现时钟分频(奇数分频，偶数分频)二分频 三分频 四分频 五分频
完整工程文件：
clkdiv.zip
//------------------------------------------------------
// File Name : clkdiv.v
// Author : ChanRa1n
// Description : clk divider
// Called by : TopModule
// Revision History : 2022-04-21
// Revision : 1.0
// Email : [email protected]
// Copyright(c) 2018-Now, MYFPGA.CN, All right reserved.
//------------------------------------------------------
module clkdiv (
input wire [0:0] Sys_clk
,input wire [0:0] Sys_rst_n
,output wire [0:0] Sig_clk_div2
,output wire [0:0] Sig_clk_div3
,output wire [0:0] Sig_clk_div4
,output wire [0:0] Sig_clk_div5
);
//------------------------------------------------------
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction
//------------------------------------------------------
//Divided by 2
reg [0:0] Sig_clk_div2_reg;
assign Sig_clk_div2 = Sig_clk_div2_reg ;
always@(posedge Sys_clk or negedge Sys_rst_n)begin
if(~Sys_rst_n)begin
Sig_clk_div2_reg <= 0;
end
else begin
Sig_clk_div2_reg <= ~Sig_clk_div2_reg;
end
end
//------------------------------------------------------
//Divided by 3
`define CLK_DIV_3 3
reg [0:0] Sig_clk_div3_p;
reg [0:0] Sig_clk_div3_n;
reg [log2(`CLK_DIV_3-1):0] Sig_clk_div3_p_cnt;
reg [log2(`CLK_DIV_3-1):0] Sig_clk_div3_n_cnt;
assign Sig_clk_div3 = Sig_clk_div3_p && Sig_clk_div3_n ;
always@(posedge Sys_clk or negedge Sys_rst_n)begin
if(~Sys_rst_n)begin
Sig_clk_div3_p <= 1;
Sig_clk_div3_p_cnt <= 0;
end
else begin
if(Sig_clk_div3_p_cnt < ( `CLK_DIV_3>>1 ))
Sig_clk_div3_p <= 0;
else
Sig_clk_div3_p <= 1;
if(Sig_clk_div3_p_cnt < `CLK_DIV_3-1)
Sig_clk_div3_p_cnt <= Sig_clk_div3_p_cnt + 1;
else
Sig_clk_div3_p_cnt <= 0;
end
end
always@(negedge Sys_clk or negedge Sys_rst_n)begin
if(~Sys_rst_n)begin
Sig_clk_div3_n <= 1;
Sig_clk_div3_n_cnt <= 0;
end
else begin
if(Sig_clk_div3_n_cnt < ( `CLK_DIV_3>>1 ))
Sig_clk_div3_n <= 0;
else
Sig_clk_div3_n <= 1;
if(Sig_clk_div3_n_cnt < `CLK_DIV_3-1)
Sig_clk_div3_n_cnt <= Sig_clk_div3_n_cnt + 1;
else
Sig_clk_div3_n_cnt <= 0;
end
end
//------------------------------------------------------
//Divided by 4
reg [0:0] Sig_clk_div4_reg;
reg [0:0] Sig_clk_div4_reg1;
assign Sig_clk_div4 = Sig_clk_div4_reg ;
always@(posedge Sys_clk or negedge Sys_rst_n)begin
if(~Sys_rst_n)begin
Sig_clk_div4_reg <= 0;
Sig_clk_div4_reg1 <= 1;
end
else begin
Sig_clk_div4_reg <= Sig_clk_div4_reg1;
Sig_clk_div4_reg1 <= ~Sig_clk_div4_reg;
end
end
//------------------------------------------------------
//Divided by 5
`define CLK_DIV_5 5
reg [0:0] Sig_clk_div5_p;
reg [0:0] Sig_clk_div5_n;
reg [log2(`CLK_DIV_5-1):0] Sig_clk_div5_p_cnt;
reg [log2(`CLK_DIV_5-1):0] Sig_clk_div5_n_cnt;
assign Sig_clk_div5 = Sig_clk_div5_p && Sig_clk_div5_n ;
always@(posedge Sys_clk or negedge Sys_rst_n)begin
if(~Sys_rst_n)begin
Sig_clk_div5_p <= 1;
Sig_clk_div5_p_cnt <= 0;
end
else begin
if(Sig_clk_div5_p_cnt < ( `CLK_DIV_5>>1 ))
Sig_clk_div5_p <= 0;
else
Sig_clk_div5_p <= 1;
if(Sig_clk_div5_p_cnt < `CLK_DIV_5-1)
Sig_clk_div5_p_cnt <= Sig_clk_div5_p_cnt + 1;
else
Sig_clk_div5_p_cnt <= 0;
end
end
always@(negedge Sys_clk or negedge Sys_rst_n)begin
if(~Sys_rst_n)begin
Sig_clk_div5_n <= 1;
Sig_clk_div5_n_cnt <= 0;
end
else begin
if(Sig_clk_div5_n_cnt < ( `CLK_DIV_5>>1 ))
Sig_clk_div5_n <= 0;
else
Sig_clk_div5_n <= 1;
if(Sig_clk_div5_n_cnt < `CLK_DIV_5-1)
Sig_clk_div5_n_cnt <= Sig_clk_div5_n_cnt + 1;
else
Sig_clk_div5_n_cnt <= 0;
end
end
endmodule
//------------------------------------------------------
// File Name : clkdiv_tb.v
// Author : ChanRa1n
// Description : Testbench file for clkdiv_tb
// Called by : Simulation
// Revision History : 2022-04-21
// Revision : 1.0
// Email : [email protected]
// Copyright(c) 2018-Now, MYFPGA.CN, All right reserved.
//------------------------------------------------------
`default_nettype wire
`timescale 1ns/1ns
module clkdiv_tb ();
reg Sys_clk;
reg Sys_rst_n;
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) Sys_clk=~Sys_clk;
clkdiv clkdiv(
.Sys_clk(Sys_clk),
.Sys_rst_n(Sys_rst_n)
);
initial begin
#1 Sys_rst_n<=1'b0;Sys_clk<=1'b0;
#(CLK_PERIOD*3) Sys_rst_n<=1;
#(CLK_PERIOD*3000);
$stop;
end
endmodule
